1. Field of the Invention
Embodiments of the present invention generally relate to methods for fabricating devices on semiconductor substrates. More specifically, the present invention relates to a method for fabricating field effect transistors and, in particular, gate dielectrics of the field effect transistors.
2. Description of the Related Art
Integrated circuits may include more than one million micro-electronic field effect transistors (e.g., complementary metal-oxide-semiconductor (CMOS) field effect transistors) that are formed on a substrate and cooperate to perform various functions within the circuit. A CMOS transistor comprises a gate structure disposed over a channel region formed between source and drain regions of the transistor. The gate structure generally comprises a gate electrode and a gate dielectric. The gate electrode is disposed over the gate dielectric and, in operation, is used to control a flow of charge carriers (i.e., electric current) in the channel region beneath the gate dielectric.
The gate dielectric is typically formed from silicon nitride (Si3N4) or silicon oxynitride (SiON). To increase the speed of the transistor, a thickness of the gate dielectric in advanced integrated circuits is selected in a range of about 20-30 angstroms or less. However, fabrication of gate structures having such ultra-thin gate dielectrics represents a challenging task. One specific problem is that present manufacturing techniques cause high leakage currents through the gate dielectric and decrease mobility of the charge carriers in the channel region due to diffusion of large amounts of nitrogen (N2) into the silicon/gate dielectric interface of the transistors. In addition, interaction of nitrogen with poly silicon of the gate electrode shifts VFB/Vt, wherein VFB is the flat-band voltage and Vt is the threshold voltage.
Therefore, there is a need in the art for an improved method for fabricating a gate dielectric of a field effect transistor.